Case-Based Synthesis of Telecommunication Architectures

As the design of systems has become more complex, promoting rapid prototyping has emerged to be an effective solution to meet the increasing time-to-market demands. Reducing the design time and cost of an electronic system are two main objectives of rapid prototyping. This paper describes a novel design flow for rapid prototyping of telecommunication systems, particularly in the application area of digital transceivers for communication links. This design method is based on an extensible library of reusable VHDL blocks and a novel facility added to the Module Manager allowing a case-based VHDL synthesis of digital architectures. The Module Manager and the library can interact easily with simulation and logic synthesis commercial tools. The purpose of this approach is also to fill in the gap between the algorithm level description of a digital signal processing application and the implementation level. We begin by comparing case-based synthesis with high-level synthesis. This is followed by an overview of the proposed design flow. An application example is then used to show the practical feasibility and current limitations of this method.